 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| LTC3568 1.8A, 4MHz, Synchronous Step-Down DC/DC Converter FEATURES DESCRIPTION The LTC(R)3568 is a constant frequency, synchronous step- down DC/DC converter. Intended for medium power applications, it operates from a 2.5V to 5.5V input voltage range and has a user configurable operating frequency up to 4MHz, allowing the use of tiny, low cost capacitors and inductors 2mm or less in height. The output voltage is adjustable from 0.8V to 5V. Internal sychronous 0.11 power switches with 2.4A peak current ratings provide high efficiency. The LTC3568's current mode architecture and external compensation allow the transient response to be optimized over a wide range of loads and output capacitors. The LTC3568 can be configured for automatic power saving Burst Mode operation to reduce gate charge losses when the load current drops below the level required for continuous operation. For reduced noise and RF interference, the SYNC/MODE pin can be configured to skip pulses or provide forced continuous operation. To further maximize battery life, the P-channel MOSFET is turned on continuously in dropout (100% duty cycle) with a low quiescent current of 60A. In shutdown, the device draws <1A. , LT, LTC and LTM are registered trademarks of Linear Technology Corporation. Burst Mode is a registered trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents including 5481178, 6580258, 6304066, 6127815, 6611131. Uses Tiny Capacitors and Inductor High Frequency Operation: Up to 4MHz Low RDS(ON) Internal Switches: 0.110 High Efficiency: Up to 96% Stable with Ceramic Capacitors Current Mode Operation for Excellent Line and Load Transient Response Short-Circuit Protected Low Dropout Operation: 100% Duty Cycle Low Shutdown Current: IQ 1A Low Quiescent Current: 60A Output Voltages from 0.8V to 5V Selectable Burst Mode(R) Operation Sychronizable to External Clock Small 3mm x 3mm, 10-Lead DFN Package APPLICATIONS Notebook Computers Digital Cameras Cellular Phones Handheld Instruments Board Mounted Power Supplies TYPICAL APPLICATION VIN 2.5V TO 5.5V 22F VIN SYNC/MODE PGOOD LTC3568 ITH 13k 1000pF 324k SHDN/RT SGND PGND 412k VFB PVIN SVIN SW 887k L1 2H Efficiency vs Load Current 100 95 EFFICIENCY POWER LOSS (mW) EFFICIENCY (%) 90 85 POWER LOSS 80 75 70 1 VIN = 3.3V VOUT = 2.5V fO = 1MHz Burst Mode OPERATION 10 100 1000 LOAD CURRENT (mA) 10 100 1000 VOUT 2.5V/1.8A 22F + 10F NOTE: IN DROPOUT, THE OUTPUT TRACKS THE INPUT VOLTAGE 3568 F01 1 10000 Figure 1. Step-Down 1.8A Regulator 3568 TA01 3568f 1 LTC3568 ABSOLUTE MAXIMUM RATINGS (Note 1) PACKAGE/ORDER INFORMATION TOP VIEW SHDN/RT SYNC/MODE SGND SW PGND 1 2 3 4 5 11 10 ITH 9 VFB 8 PGOOD 7 SVIN 6 PVIN PVIN, SVIN Voltages .................................... -0.3V to 6V VFB, ITH, SHDN/RT Voltages ......... -0.3V to (VIN + 0.3V) SYNC/MODE Voltage .................... -0.3V to (VIN + 0.3V) SW Voltage ................................. -0.3V to (VIN + 0.3V) PGOOD Voltage ........................................... -0.3V to 6V Operating Ambient Temperature Range (Note 2) ............................................... -40C to 85C Junction Temperature (Notes 5, 8) ...................... 125C Storage Temperature Range................... -65C to 125C DD PACKAGE 10-LEAD (3mm x 3mm) PLASTIC DFN TJMAX = 125C, JA = 43C/W, JC = 3C/W EXPOSED PAD (PIN 11) IS GND, MUST BE SOLDERED TO PCB ORDER PART NUMBER LTC3568EDD DD PART MARKING LCSG Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/ Consult LTC Marketing for parts specified with wider operating temperature ranges. ELECTRICAL CHARACTERISTICS SYMBOL VIN IFB VFB VLINEREG VLOADREG gm(EA) IS PARAMETER Operating Voltage Range Feedback Pin Input Current Feedback Voltage Reference Voltage Line Regulation Output Voltage Load Regulation Error Amplifier Transconductance Input DC Supply Current (Note 4) Active Mode Sleep Mode Shutdown Shutdown Threshold High Active Oscillator Resistor Oscillator Frequency Synchronization Frequency Peak Switch Current Limit Top Switch On-Resistance (Note 6) Bottom Switch On-Resistance (Note 6) ISW(LKG) VUVLO Switch Leakage Current Undervoltage Lockout Threshold The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VIN = 3.3V, RT = 324k unless otherwise specified. (Note 2) CONDITIONS (Note 3) (Note 3) VIN = 2.25V to 5V ITH = 0.36, (Note 3) ITH = 0.84, (Note 3) ITH Pin Load = 5A (Note 3) VFB = 0.75V, SYNC/MODE = 3.3V VSYNC/MODE = 3.3V, VFB = 1V VSHDN/RT = 3.3V MIN 2.25 0.784 TYP MAX 5.5 0.1 UNITS V A V %/V % % S 0.8 0.04 0.02 -0.02 800 240 62 0.1 VIN - 0.6 324k 0.816 0.2 0.2 -0.2 350 100 1 VIN - 0.4 1M 1.15 4 4 4 0.15 0.15 1 2.25 A A A V MHz MHz MHz A A V VSHDN/RT fOSC fSYNC ILIM RDS(ON) RT = 324k (Note 7) (Note 7) ITH = 1.3 VIN = 3.3V VIN = 3.3V VIN = 6V, VITH/RUN = 0V, VFB = 0V VIN Ramping Down 0.85 0.4 2.4 1 3 0.11 0.11 0.01 2 3568f 2 LTC3568 ELECTRICAL CHARACTERISTICS PGOOD RPGOOD Power Good Threshold Power Good Pull-Down On-Resistance The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VIN = 3.3V, RT = 324k unless otherwise specified. (Note 2) VFB Ramping Up, SHDN/RT = 1V VFB Ramping Down, SHDN/RT = 1V 6.8 -7.6 118 200 % % Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTC3568 is guaranteed to meet specified performance from 0C to 85C. Specifications over the -40C to 85C operating ambient termperature range are assured by design, characterization and correlation with statistical process controls. Note 3: The LTC3568 is tested in a feedback loop which servos VFB to the midpoint for the error amplifier (VITH = 0.6V). Note 4: Dynamic supply current is higher due to the internal gate charge being delivered at the switching frequency. Note 5: TJ is calculated from the ambient TA and power dissipation PD according to the following formula: TJ = TA + (PD * 43C/W) Note 6: Switch on-resistance is guaranteed by correlation to wafer level measurements. Note 7: 4MHz operation is guaranteed by design but not production tested and is subject to duty cycle limitations (see Applications Information). Note 8: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 125C when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability. TYPICAL PERFORMANCE CHARACTERISTICS Burst Mode Operation VOUT 10mV/ DIV SW 2V/DIV IL 500mA/ DIV VIN = 3.3V VOUT = 2.5V ILOAD = 100mA 10s/DIV 3568 G01 Pulse Skipping Mode VOUT 10mV/ DIV SW 2V/DIV VOUT 10mV/ DIV Forced Continuous Mode SW 2V/DIV IL 200mA/ DIV VIN = 3.3V VOUT = 2.5V ILOAD = 100mA 2s/DIV 3568 G02 IL 500mA/ DIV VIN = 3.3V VOUT = 2.5V ILOAD = 100mA 2s/DIV 3568 G03 Efficiency vs Load Current 100 95 EFFICIENCY (%) EFFICIENCY (%) 90 85 80 75 70 100 Burst Mode OPERATION 95 90 85 80 75 70 65 Efficiency vs VIN IOUT = 500mA VOUT 100mV/ DIV IOUT = 1.8A Load Step PULSE SKIP FORCED CONTINUOUS VIN = 3.3V VOUT = 2.5V CIRCUIT OF FIGURE 7 IL 1A/ DIV VOUT = 2.5V CIRCUIT OF FIGURE 7 3.0 3.5 4.0 4.5 VIN (V) 5.0 5.5 6.0 VIN = 3.3V 50s/DIV VOUT = 2.5V ILOAD = 180mA TO 1.8A 3568 G06 1 10 100 1000 LOAD CURRENT (mA) 10000 3568 G04 60 2.5 3568 G05 3568f 3 LTC3568 TYPICAL PERFORMANCE CHARACTERISTICS Load Regulation 0.6 0.5 0.4 VOUT ERROR (%) 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 1 10 100 1000 LOAD CURRENT (mA) 10000 3568 G07 Line Regulation 0.20 10 VOUT = 1.8V 0.15 0.10 VOUT ERROR (%) 0.05 0 -0.05 -0.10 -0.15 -0.20 2.0 2.5 3.0 3.5 4.0 4.5 VIN (V) 5.0 5.5 6.0 IOUT = 1.8A IOUT = 500mA FREQUENCY VARIATION (%) 8 6 4 2 0 -2 -4 -6 -8 -10 VIN = 3.3V VOUT = 1.8V Frequency vs VIN VOUT = 1.8V IOUT = 1.25A TA = 25C Burst Mode OPERATION PULSE SKIP FORCED CONTINUOUS 2 3 4 VIN (V) 5 6 3568 G09 3568 G08 Frequency Variation vs Temperature 10 8 REFERENCE VARIATION (%) 6 4 2 0 -2 -4 -6 -8 -10 -50 -25 0 25 50 75 TEMPERATURE (C) 100 125 85 EFFICIENCY (%) 95 100 Efficiency vs Frequency VIN = 3.3V VOUT = 2.5V IOUT = 500mA TA = 25C 90 0 1 2 3 FREQUENCY (MHz) 4 3568 G11 3568 G10 RDS(ON) vs VIN 120 TA = 25C 115 110 SYNCHRONOUS SWITCH RDS(ON) 105 MAIN SWITCH 100 95 90 2.5 160 150 140 130 120 110 100 90 80 70 3 3.5 4 4.5 VIN (V) 5 5.5 6 RDS(ON) vs Temperature VIN = 2.5V VIN = 3.3V RDS(ON) (m) VIN = 5V 60 -50 MAIN SWITCH SYNCHRONOUS SWITCH -25 0 25 50 75 TEMPERATURE (C) 100 125 3568 G12 3568 G13 3568f 4 LTC3568 PIN FUNCTIONS SHDN/RT (Pin 1): Combination Shutdown and Timing Resistor Pin. The oscillator frequency is programmed by connecting a resistor from this pin to ground. Forcing this pin to SVIN causes the device to be shut down. In shutdown all functions are disabled. SYNC/MODE (Pin 2): Combination Mode Selection and Oscillator Synchronization Pin. This pin controls the operation of the device. When tied to SVIN or SGND, Burst Mode operation or pulse skipping mode is selected, respectively. If this pin is held at half of SVIN, the forced continuous mode is selected. The oscillation frequency can be syncronized to an external oscillator applied to this pin. When synchronized to an external clock pulse skip mode is selected. SGND (Pin 3): The Signal Ground Pin. All small signal components and compensation components should be connected to this ground (see Board Layout Considerations). SW (Pin 4): The Switch Node Connection to the Inductor. This pin swings from PVIN to PGND. PGND (Pin 5): Main Power Ground Pin. Connect to the (-) terminal of COUT, and (-) terminal of CIN. PVIN (Pin 6): Main Supply Pin. Must be closely decoupled to PGND. SVIN (Pin 7): The Signal Power Pin. All active circuitry is powered from this pin. Must be closely decoupled to SGND. SVIN must be greater than or equal to PVIN. PGOOD (Pin 8): The Power Good Pin. This common drain logic output is pulled to SGND when the output voltage is not within 7.5% of regulation. VFB (Pin 9): Receives the feedback voltage from the external resistive divider across the output. Nominal voltage for this pin is 0.8V. ITH (Pin 10): Error Amplifier Compensation Point. The current comparator threshold increases with this control voltage. Nominal voltage range for this pin is 0V to 1.5V. Exposed Pad (Pin 11): Thermal Ground. Connect to SGND and solder to the PCB for rated thermal performance. BLOCK DIAGRAM SVIN 7 0.8V SGND 3 ITH 10 PMOS CURRENT COMPARATOR PVIN 6 VOLTAGE REFERENCE ITH LIMIT BCLAMP + - + - VFB 9 - ERROR AMPLIFIER VB + BURST COMPARATOR HYSTERESIS = 80mV OSCILLATOR SLOPE COMPENSATION 4 SW 0.74V + - + 0.86V PGOOD 8 + LOGIC NMOS COMPARATOR - - - + 5 PGND REVERSE COMPARATOR 1 SHDN/RT 2 SYNC/MODE 3568 BD 3568f 5 LTC3568 OPERATION The LTC3568 uses a constant frequency, current mode architecture. The operating frequency is determined by the value of the RT resistor or can be synchronized to an external oscillator. To suit a variety of applications, the selectable Mode pin, allows the user to trade-off noise for efficiency. The output voltage is set by an external divider returned to the VFB pin. An error amplfier compares the divided output voltage with a reference voltage of 0.8V and adjusts the peak inductor current accordingly. Overvoltage and undervoltage comparators will pull the PGOOD output low if the output voltage is not within 7.5%. Main Control Loop During normal operation, the top power switch (P-channel MOSFET) is turned on at the beginning of a clock cycle when the VFB voltage is below the the reference voltage. The current into the inductor and the load increases until the current limit is reached. The switch turns off and energy stored in the inductor flows through the bottom switch (N-channel MOSFET) into the load until the next clock cycle. The peak inductor current is controlled by the voltage on the ITH pin, which is the output of the error amplifier.This amplifier compares the VFB pin to the 0.8V reference. When the load current increases, the VFB voltage decreases slightly below the reference. This decrease causes the error amplifier to increase the ITH voltage until the average inductor current matches the new load current. The main control loop is shut down by pulling the SHDN/RT pin to SVIN. A digital soft-start is enabled after shutdown, which will slowly ramp the peak inductor current up over 1024 clock cycles or until the output reaches regulation, whichever is first. Soft-start can be lengthened by ramping the voltage on the ITH pin (see Applications Information section). Low Current Operation Three modes are available to control the operation of the LTC3568 at low currents. All three modes automatically switch from continuous operation to to the selected mode when the load current is low. To optimize efficiency, the Burst Mode operation can be selected. When the load is relatively light, the LTC3568 automatically switches into Burst Mode operation in which the PMOS switch operates intermittently based on load demand. By running cycles periodically, the switching losses which are dominated by the gate charge losses of the power MOSFETs are minimized. The main control loop is interrupted when the output voltage reaches the desired regulated value. The hysteretic voltage comparator B trips when ITH is below 0.24V, shutting off the switch and reducing the power. The output capacitor and the inductor supply the power to the load until ITH/RUN exceeds 0.31V, turning on the switch and the main control loop which starts another cycle. For lower output voltage ripple at low currents, pulse skipping mode can be used. In this mode, the LTC3568 continues to switch at a constant frequency down to very low currents, where it will eventually begin skipping pulses. Finally, in forced continuous mode, the inductor current is constantly cycled which creates a fixed output voltage ripple at all output current levels. This feature is desirable in telecommunications since the noise is at a constant frequency and is thus easy to filter out. Another advantage of this mode is that the regulator is capable of both sourcing current into a load and sinking some current from the output. Dropout Operation When the input supply voltage decreases toward the output voltage, the duty cycle increases to 100% which is the dropout condition. In dropout, the PMOS switch is turned on continuously with the output voltage being equal to the input voltage minus the voltage drops across the internal P-channel MOSFET and the inductor. Low Supply Operation The LTC3568 incorporates an undervoltage lockout circuit which shuts down the part when the input voltage drops below about 2V. 3568f 6 LTC3568 APPLICATIONS INFORMATION A general LTC3568 application circuit is shown in Figure 5. External component selection is driven by the load requirement, and begins with the selection of the inductor L1. Once L1 is chosen, CIN and COUT can be selected. Operating Frequency Selection of the operating frequency is a tradeoff between efficiency and component size. High frequency operation allows the use of smaller inductor and capacitor values. Operation at lower frequencies improves efficiency by reducing internal gate charge losses but requires larger inductance values and/or capacitance to maintain low output ripple voltage. The operating frequency, fO, of the LTC3568 is determined by an external resistor that is connected between the RT pin and ground. The value of the resistor sets the ramp current that is used to charge and discharge an internal timing capacitor within the oscillator and can be calculated by using the following equation: RT = 9.78 * 1011( fO ) -1.08 A reasonable starting point for setting ripple current is IL = 0.4 * IOUT, where IOUT is the maximum output current. The largest ripple current IL occurs at the maximum input voltage. To guarantee that the ripple current stays below a specified maximum, the inductor value should be chosen according to the following equation: L= VOUT f O* IL V * 1 - OUT V IN(MAX) The inductor value will also have an effect on Burst Mode operation. The transition from low current operation begins when the peak inductor current falls below a level set by the burst clamp. Lower inductor values result in higher ripple current which causes this to occur at lower load currents. This causes a dip in efficiency in the upper range of low current operation. In Burst Mode operation, lower inductance values will cause the burst frequency to increase. 4.5 4.0 3.5 FREQUENCY (MHz) 3.0 2.5 2.0 1.5 1.0 0.5 0 0 500 RT (k) 3568 F02 ( ) TA = 25C or can be selected using Figure 2. The maximum usable operating frequency is limited by the minimum on-time and the duty cycle. This can be calculated as: fO(MAX) 6.67 * (VOUT / VIN(MAX)) (MHz) The minimum frequency is limited by leakage and noise coupling due to the large resistance of RT. Inductor Selection Although the inductor does not influence the operating frequency, the inductor value has a direct effect on ripple current. The inductor ripple current IL decreases with higher inductance and increases with higher VIN or VOUT: IL = VOUT VOUT * 1- f O* L V IN 1000 1500 Figure 2. Frequency vs RT Inductor Core Selection Different core materials and shapes will change the size/current and price/current relationship of an inductor. Toroid or shielded pot cores in ferrite or permalloy materials are small and don't radiate much energy, but generally cost more than powdered iron core inductors with similar electrical characteristics. The choice of which style inductor to use often depends more on the price vs size requirements and any radiated field/EMI requirements than on what the LTC3568 requires to operate. Table 1 shows some typical surface 3568f Accepting larger values of IL allows the use of low inductances, but results in higher output voltage ripple, greater core losses, and lower output current capability. 7 LTC3568 APPLICATIONS INFORMATION mount inductors that work well in LTC3568 applications. Table 1. Representative Surface Mount Inductors MANUFACTURER PART NUMBER Toko Toko Toko Coilcraft Sumida Sumida Sumida TDK A915Y-2R0M (D53LC-A) A918CY-2R0M (D62LCB) D01608C-222 CDRH2D18/HP1R7 CDRH4D282R2 CDC5D232R2 VLCF4020T-1R8N1R9 MAX DC VALUE CURRENT DCR HEIGHT 2.05A 3.3A 2.33A 2.3A 1.8A 2.04A 2.16A 1.97A 3.2A 2.9A 2.37A 49m 22m 24m 70m 35m 23m 46m 2mm 3mm 2mm 3mm 2mm 3mm 2mm 2H 2H 2.2H 1.7H 2.2H 2.2H 1.8H 2.2H 2.2H 2H 0.1F to 1F ceramic capacitor is also recommended on VIN for high frequency decoupling, when not using an all ceramic capacitor solution. Output Capacitor (COUT) Selection The selection of COUT is driven by the required ESR to minimize voltage ripple and load step transients. Typically, once the ESR requirement is satisfied, the capacitance is adequate for filtering. The output ripple (VOUT) is determined by: 1 VOUT IL ESR + 8fO C OUT where f = operating frequency, COUT = output capacitance and IL = ripple current in the inductor. The output ripple is highest at maximum input voltage since IL increases with input voltage. With IL = 0.4 * IOUT the output ripple will be less than 100mV at maximum VIN and fO = 1MHz with: ESRCOUT < 130m Once the ESR requirements for COUT have been met, the RMS current rating generally far exceeds the IRIPPLE(P-P) requirement, except for an all ceramic solution. In surface mount applications, multiple capacitors may have to be paralleled to meet the capacitance, ESR or RMS current handling requirement of the application. Aluminum electrolytic, special polymer, ceramic and dry tantulum capacitors are all available in surface mount packages. The OS-CON semiconductor dielectric capacitor available from Sanyo has the lowest ESR(size) product of any aluminum electrolytic at a somewhat higher price. Special polymer capacitors, such as Sanyo POSCAP, offer very low ESR, but have a lower capacitance density than other types. Tantalum capacitors have the highest capacitance density, but it has a larger ESR and it is critical that the capacitors are surge tested for use in switching power supplies. An excellent choice is the AVX TPS series of surface mount tantalums, avalable in case heights ranging from 2mm to 4mm. Aluminum electrolytic capacitors have a significantly larger ESR, and is often used in extremely cost-sensitive applications provided that consideration is given to ripple current ratings and long term reliability. 3568f A914BYW-2R2M (D52LC) 2.2H 30m 2.5mm 29m 3.2mm 32m 2.8mm 45m 1.45mm Taiyo Yuden N06DB2R2M Taiyo Yuden N05DB2R2M Cooper SD14-2R0 Catch Diode Selection A catch diode is not necessary. Input Capacitor (CIN) Selection In continuous mode, the input current of the converter is a square wave with a duty cycle of approximately VOUT/VIN. To prevent large voltage transients, a low equivalent series resistance (ESR) input capacitor sized for the maximum RMS current must be used. The maximum RMS capacitor current is given by: IRMS IMAX VOUT (VIN - VOUT ) VIN where the maximum average output current IMAX equals the peak current minus half the peak-to-peak ripple current, IMAX = ILIM - IL/2. This formula has a maximum at VIN = 2VOUT, where IRMS = IOUT/2. This simple worst case is commonly used to design because even significant deviations do not offer much relief. Note that capacitor manufacturer's ripple current ratings are often based on only 2000 hours lifetime. This makes it advisable to further derate the capacitor, or choose a capacitor rated at a higher temperature than required. Several capacitors may also be paralleled to meet the size or height requirements of the design. An additional 8 LTC3568 APPLICATIONS INFORMATION Ceramic capacitors have the lowest ESR and cost but also have the lowest capacitance density, a high voltage and temperature coefficient and exhibit audible piezoelectric effects. In addition, the high Q of ceramic capacitors along with trace inductance can lead to significant ringing. Other capacitor types include the Panasonic specialty polymer (SP) capacitors. In most cases, 0.1F to 1F of ceramic capacitors should also be placed close to the LTC3568 in parallel with the main capacitors for high frequency decoupling. Ceramic Input and Output Capacitors Higher value, lower cost ceramic capacitors are now becoming available in smaller case sizes. These are tempting for switching regulator use because of their very low ESR. Unfortunately, the ESR is so low that it can cause loop stability problems. Solid tantalum capacitor ESR generates a loop "zero" at 5kHz to 50kHz that is instrumental in giving acceptable loop phase margin. Ceramic capacitors remain capacitive to beyond 300kHz and ususally resonate with their ESL before ESR becomes effective. Also, ceramic caps are prone to temperature effects which requires the designer to check loop stability over the operating temperature range. To minimize their large temperature and voltage coefficients, only X5R or X7R ceramic capacitors should be used. A good selection of ceramic capacitors is available from Taiyo Yuden, TDK and Murata. Great care must be taken when using only ceramic input and output capacitors. When a ceramic capacitor is used at the input and the power is being supplied through long wires, such as from a wall adapter, a load step at the output can induce ringing at the VIN pin. At best, this ringing can couple to the output and be mistaken as loop instability. At worst, the ringing at the input can be large enough to damage the part. Since the ESR of a ceramic capacitor is so low, the input and output capacitor must instead fulfill a charge storage requirement. During a load step, the output capacitor must instantaneously supply the current to support the load until the feedback loop raises the switch current enough to support the load. The time required for the feedback loop to respond is dependent on the compensation components and the output capacitor size. Typically, 3 to 4 cycles are required to respond to a load step, but only in the first cycle does the output drop linearly. The output droop, VDROOP, is usually about 2 to 3 times the linear drop of the first cycle. Thus, a good place to start is with the output capacitor size of approximately: C OUT 2.5 IOUT fO * VDROOP More capacitance may be required depending on the duty cycle and load step requirements. In most applications, the input capacitor is merely required to supply high frequency bypassing, since the impedance to the supply is very low. A 22F ceramic capacitor is usually enough for these conditions. Setting the Output Voltage The LTC3568 develops a 0.8V reference voltage between the feedback pin, VFB, and the signal ground as shown in Figure 5. The output voltage is set by a resistive divider according to the following formula: R2 VOUT 0.8V 1 + R1 Keeping the current small (<5A) in these resistors maximizes efficiency, but making them too small may allow stray capacitance to cause noise problems and reduce the phase margin of the error amp loop. To improve the frequency response, a feed-forward capacitor CF may also be used. Great care should be taken to route the VFB line away from noise sources, such as the inductor or the SW line. Shutdown and Soft-Start The SHDN/RT pin is a dual purpose pin that sets the oscillator frequency and provides a means to shut down the LTC3568. This pin can be interfaced with control logic in several ways, as shown in Figure 3(a) and Figure 3(b). The ITH pin is primarily for loop compensation, but it can also be used to increase the soft-start time. Soft start reduces surge currents from VIN by gradually increasing the peak inductor current. Power supply sequencing can also be accomplished using this pin. The LTC3568 has an 3568f 9 LTC3568 APPLICATIONS INFORMATION SHDN/RT RT RUN SHDN/RT RT SVIN 1M RUN (3a) RUN OR VIN R1 D1 ITH RC (3b) to ground, pulse skipping operation is selected which provides the lowest output voltage and current ripple at the cost of low current efficiency. Applying a voltage between SVIN - 1V and 1V, results in forced continuous mode, which creates a fixed output ripple and is capable of sinking some current (about 1/2IL). Since the switching noise is constant in this mode, it is also the easiest to filter out. In many cases, the output voltage can be simply connected to the SYNC/MODE pin, giving the forced continuous mode, except at startup. The LTC3568 can also be synchronized to an external clock signal by the SYNC/MODE pin. The internal oscillator frequency should be set to 20% lower than the external clock frequency to ensure adequate slope compensation, since slope compensation is derived from the internal oscillator. During synchronization, the mode is set to pulse skipping and the top switch turn on is synchronized to the rising edge of the external clock. Checking Transient Response The OPTI-LOOP compensation allows the transient response to be optimized for a wide range of loads and output capacitors. The availability of the ITH pin not only allows optimization of the control loop behavior but also provides a DC-coupled and AC filtered closed loop response test point. The DC step, rise time and settling at this test point truly reflects the closed loop response. Assuming a predominantly second order system, phase margin and/or damping factor can be estimated using the percentage of overshoot seen at this pin. The bandwidth can also be estimated by examining the rise time at the pin. The ITH external components shown in the Figure 1 circuit will provide an adequate starting point for most applications. The series R-C filter sets the dominant pole-zero loop compensation. The values can be modified slightly (from 0.5 to 2 times their suggested values) to optimize transient response once the final PC layout is done and the particular output capacitor type and value have been determined. The output capacitors need to be selected because the various types and values determine the loop feedback factor gain and phase. An output current pulse of 20% to 100% of full load current having a rise time of 1s to 10s will produce output voltage and ITH pin waveforms 3568f C1 CC 3568 F03 (3c) Figure 3. SHDN/RT Pin Interfacing and External Soft-Start internal digital soft-start which steps up a clamp on ITH over 1024 clock cycles, as can be seen in Figure 4. The soft-start time can be increased by ramping the voltage on ITH during start-up as shown in Figure 3(c). As the voltage on ITH ramps through its operating range the internal peak current limit is also ramped at a proportional linear rate. VIN 5V/DIV VOUT 1V/DIV IL 1A/DIV 3568 F04 VIN = 3.3V VOUT = 2.5V ILOAD = 1.8A 400s/DIV Figure 4. Digital Soft-Start Mode Selection and Frequency Synchronization The SYNC/MODE pin is a multipurpose pin which provides mode selection and frequency synchronization. Connecting this pin to VIN enables Burst Mode operation, which provides the best low current efficiency at the cost of a higher output voltage ripple. When this pin is connected 10 LTC3568 APPLICATIONS INFORMATION that will give a sense of the overall loop stability without breaking the feedback loop. Switching regulators take several cycles to respond to a step in load current. When a load step occurs, VOUT immediately shifts by an amount equal to ILOAD * ESR, where ESR is the effective series resistance of COUT. ILOAD also begins to charge or discharge COUT generating a feedback error signal used by the regulator to return VOUT to its steady-state value. During this recovery time, VOUT can be monitored for overshoot or ringing that would indicate a stability problem. The initial output voltage step may not be within the bandwidth of the feedback loop, so the standard second order overshoot/DC ratio cannot be used to determine phase margin. The gain of the loop increases with R and the bandwidth of the loop increases with decreasing C. If R is increased by the same factor that C is decreased, the zero frequency will be kept the same, thereby keeping the phase the same in the most critical frequency range of the feedback loop. In addition, a feedforward capacitor CF can be added to improve the high frequency response, as shown in Figure 5. Capacitor CF provides phase lead by creating a high frequency zero with R2 which improves the phase margin. The output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance. For a detailed explanation of optimizing the compensation components, including a review of control loop theory, refer to Linear Technology Application Note 76. Although a buck regulator is capable of providing the full output current in dropout, it should be noted that as the input voltage VIN drops toward VOUT, the load step capability does decrease due to the decreasing voltage across the inductor. Applications that require large load step capability near dropout should use a different topology such as SEPIC, Zeta or single inductor, positive buck/boost. In some applications, a more severe transient can be caused by switching in loads with large (>1uF) input capacitors. The discharged input capacitors are effectively put in parallel with COUT, causing a rapid drop in VOUT. No regulator can deliver enough current to prevent this problem, if the switch connecting the load has low resistance and is driven quickly. The solution is to limit the turn-on speed of the load switch driver. A hot swap controller is designed specifically for this purpose and usually incorporates current limiting, short-circuit protection, and soft-starting. Efficiency Considerations The percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Percent efficiency can be expressed as: %Efficiency = 100% - (L1 + L2 + L3 + ...) where L1, L2, etc. are the individual losses as a percentage of input power. Although all dissipative elements in the circuit produce losses, four main sources usually account for most of VIN 2.5V TO 5.5V + C6 CIN C8 PGND PGND R6 SVIN PVIN LTC3568 SYNC/MODE ITH VFB SHDN/RT RC SGND PGND PGOOD SW SGND R5 PGOOD L1 CF + COUT C5 VOUT SGND CITH R1 RT R2 PGND PGND CC SGND SGND GND SGND SGND 3568 F05 Figure 5. LTC3568 General Schematic 3568f 11 LTC3568 APPLICATIONS INFORMATION the losses in LTC3568 circuits: 1) LTC3568 VIN current, 2) switching losses, 3) I2R losses, 4) other losses. 1) The VIN current is the DC supply current given in the electrical characteristics which excludes MOSFET driver and control currents. VIN current results in a small loss that increases with VIN, even at no load. 2) The switching current is the sum of the MOSFET driver and control currents. The MOSFET driver current results from switching the gate capacitance of the power MOSFETs. Each time a MOSFET gate is switched from low to high to low again, a packet of charge dQ moves from VIN to ground. The resulting dQ/dt is a current out of VIN that is typically much larger than the DC bias current. In continuous mode, IGATECHG = fO(QT + QB), where QT and QB are the gate charges of the internal top and bottom MOSFET switches. The gate charge losses are proportional to VIN and thus their effects will be more pronounced at higher supply voltages. 3) I2R Losses are calculated from the DC resistances of the internal switches, RSW, and external inductor, RL. In continuous mode, the average output current flowing through inductor L is "chopped" between the internal top and bottom switches. Thus, the series resistance looking into the SW pin is a function of both top and bottom MOSFET RDS(ON) and the duty cycle (DC) as follows: RSW = (RDS(ON)TOP)(DC) + (RDS(ON)BOT)(1 - DC) The RDS(ON) for both the top and bottom MOSFETs can be obtained from the Typical Performance Characteristics curves. Thus, to obtain I2R losses: I2R losses = IOUT2(RSW + RL) 4) Other "hidden" losses such as copper trace and internal battery resistances can account for additional efficiency degradations in portable systems. It is very important to include these "system" level losses in the design of a system. The internal battery and fuse resistance losses can be minimized by making sure that CIN has adequate charge storage and very low ESR at the switching frequency. Other losses including diode conduction losses during dead-time and inductor core losses generally account for less than 2% total additional loss. Thermal Considerations In a majority of applications, the LTC3568 does not dissipate much heat due to its high efficiency. However, in applications where the LTC3568 is running at high ambient temperature with low supply voltage and high duty cycles, such as in dropout, the heat dissipated may exceed the maximum junction temperature of the part. If the junction temperature reaches approximately 150C, both power switches will be turned off and the SW node will become high impedance. To avoid the LTC3568 from exceeding the maximum junction temperature, the user will need to do some thermal analysis. The goal of the thermal analysis is to determine whether the power dissipated exceeds the maximum junction temperature of the part. The temperature rise is given by: TRISE = PD * JA where PD is the power dissipated by the regulator and JA is the thermal resistance from the junction of the die to the ambient temperature. The junction temperature, TJ, is given by: TJ = TRISE + TAMBIENT As an example, consider the case when the LTC3568 is in dropout at an input voltage of 3.3V with a load current of 1.8A with a 70C ambient temperature. From the Typical Performance Characteristics graph of Switch Resistance, the RDS(ON) resistance of the P-channel switch is 0.125. Therefore, power dissipated by the part is: PD = I2 * RDS(ON) = 405mW The DFN package junction-to-ambient thermal resistance, JA is 43C/W. Therefore, the junction temperature of the regulator operating in a 70C ambient temperature is approximately: TJ = 0.405 * 43 + 70 = 87.4C Remembering that the above junction temperature is obtained from an RDS(ON) at 70C, we might recalculate the junction temperature based on a higher RDS(ON) since it increases with temperature. However, we can safely assume that the actual junction temperature will not exceed the absolute maximum junction temperature of 125C. 3568f 12 LTC3568 APPLICATIONS INFORMATION Design Example As a design example, consider using the LTC3568 in a typical application with VIN = 5V. The load requires a maximum of 1.8A in active mode and 10mA in standby mode. The output voltage is VOUT = 2.5V. Since the load still needs power in standby, Burst Mode operation is selected for good low load efficiency. First, calculate the timing resistor: R T = 9.78 * 1011 (1MHz ) -1.08 The closest standard value is 22F plus 10F. Since the supply's output impedance is very low, CIN is typically a 22F. In noisy environments, decoupling SVIN from PVIN with an R6/C8 filter of 1/0.1F may help, but is typically not needed. The output voltage can now be programmed by choosing the values of R1 and R2. To maintain high efficiency, the current in these resistors should be kept small. Choosing 2A with the 0.8V feedback voltage makes R1~400k. A close standard 1% resistor is 412k and R2 is then 887k. The compensation should be optimized for these components by examining the load step response but a good place to start for the LTC3568 is with a 13k and 1000pF filter. The output capacitor may need to be increased depending on the actual undershoot during a load step. The PGOOD pin is a common drain output and requires a pull-up resistor. A 100k resistor is used for adequate speed. Figure 1 shows the complete schematic for this design example. Board Layout Considerations When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the LTC3568. These items are also illustrated graphically in the layout diagram of Figure 6. Check the following in your layout: = 323.8k Use a standard value of 324k. Next, calculate the inductor value for about 40% ripple current at maximum VIN: L= 2.5V 2.5V * 1- = 1.7H 1MHz * 720mA 5V Choosing the closest inductor from a vendor of 2H, results in a maximum ripple current of: IL = 2.5V 2.5V * 1- = 625mA 1MHz * 2 5V For cost reasons, a ceramic capacitor will be used. COUT selection is then based on load step droop instead of ESR requirements. For a 5% output droop: COUT 2.5 1.8 A = 36F 1MHz * (5% * 2.5V) CIN VIN PVIN R5 PGOOD C4 R2 R1 R3 C3 SVIN LTC3568 PGOOD VFB ITH PGND SW SGND COUT L1 VOUT VIN SYNC/MODE SHDN/RT PS BM RT 3568 F06 BOLD LINES INDICATE HIGH CURRENT PATHS Figure 6. LTC3568 Layout Diagram (See Board Layout Checklist) 3568f 13 LTC3568 APPLICATIONS INFORMATION 1. Does the capacitor CIN connect to the power VIN (Pin 6) and power GND (Pin 5) as close as possible? This capacitor provides the AC current to the internal power MOSFETs and their drivers. 2. Are the COUT and L1 closely connected? The (-) plate of COUT returns current to PGND and the (-) plate of CIN. 3. The resistor divider, R1 and R2, must be connected between the (+) plate of COUT and a ground line terminated near SGND (Pin 3). The feedback signal VFB should be routed away from noisy components and traces, such as the SW line (Pin 4), and its trace should be minimized. 4. Keep sensitive components away from the SW pin. The input capacitor CIN, the compensation capacitor CC and CITH and all the resistors R1, R2, RT, and RC should be routed away from the SW trace and the inductor L1. 5. A ground plane is preferred, but if not available, keep the signal and power grounds segregated with small signal components returning to the SGND pin at one point which is then connected to the PGND pin. 6. Flood all unused areas on all layers with copper. Flooding with copper will reduce the temperature rise of power components. These copper areas should be connected to one of the input supplies: PVIN, PGND, SVIN or SGND. TYPICAL APPLICATIONS VIN 2.5V TO 5.5V C1 22F PGND SVIN BM FC PS RS2 1M R3 13k C3 1000pF SGND SGND GND RS1 1M ITH SGND PVIN LTC3568 SYNC/MODE R5 100k PGOOD PGOOD SW L1 2H R2 887K VFB SHDN/RT 3.3V PGND R4 324k R1A 280k R1B 412k 2.5V 1.8V C4 22pF R1C 698k VOUT 1.8V/2.5V/3.3V AT 1.8A C2 22F x2 3568 F07a SGND PGND NOTE: IN DROPOUT, THE OUTPUT TRACKS THE INPUT VOLTAGE C1, C2: TAIYO YUDEN JMK325BJ226MM L1: TOKO A915AY-2ROM (D53LC SERIES) Figure 7. General Purpose Buck Regulator Using Ceramic Capacitors Efficiency vs Load Current 100 95 EFFICIENCY (%) 90 85 80 75 70 Burst Mode OPERATION PULSE SKIP FORCED CONTINUOUS VIN = 3.3V VOUT = 2.5V CIRCUIT OF FIGURE 7 1 10 100 1000 LOAD CURRENT (mA) 10000 3568 F07b 3568f 14 LTC3568 TYPICAL APPLICATIONS Low Output Voltage, 2mm Height Buck Regulator VIN 2.5V TO 5.5V 95 C1 22F PGND RS1 1M RS2 1M R3 13k C3 1000pF R5 100k PGOOD SW LTC3568 SYNC/MODE PS VFB ITH SHDN/RT R4 324k GND C1: TAIYO YUDEN JMK325BJ226MM C2: TAIYO YUDEN JMK325BJ476MM L1: SUMIDA CDRH2D18/HP1R7 SGND SGND PGND 1.8V R1A 316k 1.5V R1B 453k 1.2V R2 402k L1 1.7H PGOOD C4 47pF VOUT 1.2V/1.5V/1.8V AT 1.8A VOUT = 1.8V 90 EFFICIENCY (%) Efficiency vs Load Current PVIN SVIN BM FC C2 47F x2 85 VOUT = 1.2V 80 VOUT = 1.5V 75 VIN = 3.3V Burst Mode OPERATION fO = 1MHz 1 10 100 1000 LOAD CURRENT (mA) 10000 3568 TA05 SGND R1C 787k 3568 TA04 70 PACKAGE DESCRIPTION DD Package 10-Lead Plastic DFN (3mm x 3mm) (Reference LTC DWG # 05-08-1699) R = 0.115 TYP 6 0.675 0.05 0.38 0.10 10 3.50 0.05 1.65 0.05 2.15 0.05 (2 SIDES) PACKAGE OUTLINE 0.25 0.05 0.50 BSC 2.38 0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2). CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE PIN 1 TOP MARK (SEE NOTE 6) 3.00 0.10 (4 SIDES) 1.65 0.10 (2 SIDES) (DD) DFN 1103 5 0.200 REF 0.75 0.05 2.38 0.10 (2 SIDES) 1 0.25 0.05 0.50 BSC 0.00 - 0.05 BOTTOM VIEW--EXPOSED PAD 3568f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 15 LTC3568 TYPICAL APPLICATION 1mm Height, 2MHz, Li-Ion to 1.8V Converter VIN 2.5V TO 4.2V 95 VIN = 2.7V C1 10F x2 R5 100k PVIN SVIN LTC3568 SYNC/MODE ITH C7 47pF R3 10k C3 1000pF SGND PGND VFB SHDN/RT R4 154k R1 698k R2 887k PGOOD SW L1 1H PGOOD C4 22pF EFFICIENCY (%) VOUT 1.8V AT 1.8A 90 85 80 75 70 65 3568 TA02 Efficiency vs Load Current C2 10F x3 VIN = 4.2V VIN = 3.6V C1, C2: MURATA GRM319R60J106KE01B L1: COOPER SD10-1R0 60 1 VOUT = 1.8V fO = 2MHz 10 100 1000 LOAD CURRENT (mA) 10000 3568 TA03 RELATED PARTS PART NUMBER LTC3406/LTC3406B LTC3407/LTC3407-2 LTC3410/LTC3410B LTC3411 LTC3412 DESCRIPTION 600mA (IOUT), 1.5MHz, Synchronous Step-Down DC/DC Converter Dual 600mA/800mA (IOUT), 1.5MHz/2.25MHz, Synchronous Step-Down DC/DC Converter 300mA (IOUT), 2.25MHz, Synchronous Step-Down DC/DC Converter 1.25A (IOUT), 4MHz, Synchronous Step-Down DC/DC Converter 2.5A (IOUT), 4MHz, Synchronous Step-Down DC/DC Converter COMMENTS 96% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.6V, IQ = 20A, ISD <1A, ThinSOT Package 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.6V, IQ = 40A, ISD <1A, MS10E and DFN Packages 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.8V, IQ = 26A, ISD <1A, SC70 Package 96% Efficiency, VIN: 2.6V to 5.5V, VOUT(MIN) = 0.8V, IQ = 60A, ISD <1A, MS10 and DFN Packages 96% Efficiency, VIN: 2.6V to 5.5V, VOUT(MIN) = 0.8V, IQ = 62A, ISD <1A, TSSOP-16E and QFN Packages 95% Efficiency, VIN: 1.8V to 5.5V, VOUT(MIN): 2V to 5V, IQ = 16A, ISD <1A, ThinSOT and DFN Packages 95% Efficiency, VIN: 2.4V to 5.5V, VOUT(MIN): 2.4V to 5.25V, IQ = 35A, ISD <1A, MS10 and DFN Packages 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.6V, IQ = 26A, ISD <1A, DFN Package 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.8V, IQ = 70A, ISD <1A, QFN Package 96% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.6V, IQ = 40A, ISD <1A, DFN Package 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.6V, IQ = 40A, ISD <1A, MS10E and DFN Packages 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.6V, IQ = 16A, ISD <1A, ThinSOT Package LTC3531/LTC3531-3/ 200mA (IOUT), 1.5MHz, Synchronous Buck-Boost DC/DC Converter LTC3531-3.3 LTC3532 LTC3542 LTC3544 LTC3547/LTC3547B 500mA (IOUT), 2MHz, Synchronous Buck-Boost DC/DC Converter 500mA (IOUT), 2.25MHz, Synchronous Step-Down DC/DC Converter Quad 300mA + 2x 200mA + 100mA 2.25MHz, Synchronous Step-Down DC/DC Converter Dual 300mA 2.25MHz, Synchronous Step-Down DC/DC Converter LTC3548/LTC3548-1/ Dual 400mA and 800mA (IOUT), 2.25MHz, Synchronous Step-Down DC/DC Converter LTC3548-2 LTC3560 800mA (IOUT), 2.25MHz, Synchronous Step-Down DC/DC Converter ThinSOT is a trademark of Linear Technology Corporation. 3568f 16 Linear Technology Corporation (408) 432-1900 FAX: (408) 434-0507 LT 0407 * PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 www.linear.com (c) LINEAR TECHNOLOGY CORPORATION 2007 |
Price & Availability of LTC3568EDD
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |